1. Field
Exemplary embodiments of the present invention relate to a fail address storage circuit, a redundancy control circuit, a method for storing a fail address, and a method for controlling redundancy.
2. Description of the Related Art
Generally, when a semiconductor memory device has one or more defective memory cells, the memory device may be discarded as defective products. Therefore, redundancy using reserved memory cells that are arranged in a semiconductor memory device to compensate for defective memory cells is used.
When a process of fabricating a wafer ends, defective memory cells are detected by a test and are programmed by performing fuse cutting. Positional information of the defective memory cells (that is, an address at which the fuse is cut) is stored such that redundancy memory cells are prepared so as to replace the defective memory cells.
FIG. 1 is a configuration diagram of a redundancy control circuit in accordance with the related art.
As illustrated in FIG. 1, the redundancy control circuit is configured to include a row address storage unit 110, a column address storage unit 120, a row address comparator 130, a column address comparator 140, and a redundancy controller 150.
Hereinafter, an operation of the redundancy control circuit will be described with reference to FIG. 1.
The row address storage unit 110 and the column address storage unit 120 each include a plurality of fuses. One of the plurality of fuses is cut according to whether the fail address is stored in the row address storage unit 110, where the cut fuse is referred to as ‘enable fuse’. For example, when the ‘enable fuse’ of the plurality of fuses of the row address storage unit 110 is cut, a value of the fail address (row address) is stored in the remaining fuses and when the ‘enable fuse’ is not cut, the value of the fail address is not stored in the remaining fuses. It is determined whether a row enable signal REN is activated according to whether the ‘enable fuse’ is cut. Each bit of the fail address is stored in the remaining fuse. Hereinafter, a row redundancy operation will be described.
The row address storage unit 110 is stored with the row address (fail address) that corresponds to a memory cell to be repaired. The fail address is stored and thus, the ‘enable fuse’ included in the row address storage unit 110 is cut. Hereinafter, a value stored in the row address storage unit 110 is referred to as a row address FRA<0:N>.
The row address storage unit 110 outputs the row address FRA<0:N> stored therein and activates the row enable signal REN since the ‘enable fuse’ is cut.
The row address comparator 130 compares an address RA<0:N> (hereinafter, referred to as an input row address RA<0:N>) input from the outside with a row address FRA<0:N> (hereinafter, referred to as a row address FRA<0:N>) stored in the row address storage unit 110 to generate comparison information RCMP<0:N>. Each bit of the comparison information RCMP<0:N> is activated when the corresponding bits of each bit RA<0> to RA<N> of the input row address and each bit FRA<0> to FRA<N> of the row address are equal to one another. For example, when a first bit RA<0> of the input row address is equal to a first bit FRA<0> of the row address, a first bit RCMP<0> of the comparison information is activated. Therefore, when the input row address RA<0:N> is completely equal to the row address FRA<0:N>, all the bits RCMP<0> to RCMP<N> of the comparison information are activated.
The redundancy controller 150 controls a row redundancy operation in response to the row enable signal REN and the comparison information RCMP<0:N>. When the row enable signal REN and all the bits RCMP<0> to RCMP<N> of the comparison information are activated (that is, when the row enable signal REN is activated and values of all of the corresponding bits of each bit RA<0> to RA<N> and each bit FRA<0> to FRA<N> of the row address are equal to one another), a row redundancy control signal RCON is activated. When the row redundancy control signal RCON is activated, redundancy word lines are activated, instead of original word lines corresponding to the input row address RA<0:N>.
The column redundancy operation is approximately the same as the above-mentioned row redundancy operation. The ‘enable fuse’ of the plurality of fuses included in the column address storage unit 120 is cut according to whether the fail address is stored in the column address storage unit 120. Further, a column address signal CEN is activated or inactivated according to whether the ‘enable fuse’ is cut. The column address comparator 140 compares an input column address CA<0:M> with a column address FCA<0:M> (hereinafter, referred to as a column address FCA<0:M>) stored in the column address storage unit 120 to generate comparison information CCMP<0:M>. The redundancy controller 150 activates or inactivates a control signal CCON in response to the column enable signal CEN and the comparison information CCMP<0:M>. Here, when the column enable signal CEN is activated and the input column address CA<0:M> is completely equal to the column address FCA<0:M> (when all the bits CCMP<0> to CCMP<M> are activated), the column redundancy control signal CCON is activated. When the column redundancy control signal CCON is activated, data of the memory cells connected to the redundancy bit lines are accessed, instead of the original bit lines corresponding to the input column address CA<0:N>.
The redundancy control circuit includes a plurality of row/column address storage units 110 and 130 so as to store a plurality of failed row/column addresses. However, the row address storage unit 110 may store the row address only and the column address storage unit 130 may store the column address only. Therefore, even though the values of the row address are equal to the values of the column address and may be stored in a single address storage unit, the values end up being separately stored in the row address storage unit and column address storage unit, respectively. Here, the values of the row address are equal to the values of the column address when values of the corresponding bits of the row address and the column address are equal to one another.
As a result, flexibility of the redundancy operation may be degraded and the address storage units 110 and 130 may not be efficiently used.